Digital verification engineer

Location:Shanghai/Beijing/Shenzhen/Chengdu/Xi'an

Responsibilities:
1. Verification of Block level or SoC level design using random methodologies Test Planning, Implementation and Execution.
2. Develop System Verilog (UVM) random sequences and methods.
3. Maintain and Interface with existing random generators, models Integration of random modules to various testbenches.
4. Executing verification through directed and random tests for its functionality and interface protocols and tracking bug reports.
5. Creation of the needed test libraries, simulation models. Debugging regression failures and identify the cause.
Key skills & knowledge:
1. Strong documentation and communication skills.
2. Complex IP/ SOC Design Verification, direct experience in IP/SOC
3. Good knowledge of SystemVerilog and UVM.
4. Good knowledge of Verilog/C/C++/System C is a plus.
5. Verification insights into random techniques.
6. Verification of large scale ASICs.
7. Strong scripting languages (Perl, C Shell, Makefile, ) experience.
8. Be good at English communication.