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上海芯海集成电路设计有限公司

Digital verification engineer

  • 24万-48万/年
  • 上海
  • |
  • 3年以上
  • |
  • 本科
  • |
  • 全职

职位诱惑: 五险一金,福利好,老板nice

发布时间: 2017-03-24发布

职位描述

Location:Shanghai/Beijing/Shenzhen/Chengdu/Xi'an

Responsibilities:
1. Verification of Block level or SoC level design using random methodologies Test Planning, Implementation and Execution.
2. Develop System Verilog (UVM) random sequences and methods.
3. Maintain and Interface with existing random generators, models Integration of random modules to various testbenches.
4. Executing verification through directed and random tests for its functionality and interface protocols and tracking bug reports.
5. Creation of the needed test libraries, simulation models. Debugging regression failures and identify the cause.
Key skills & knowledge:
1. Strong documentation and communication skills.
2. Complex IP/ SOC Design Verification, direct experience in IP/SOC
3. Good knowledge of SystemVerilog and UVM.
4. Good knowledge of Verilog/C/C++/System C is a plus.
5. Verification insights into random techniques.
6. Verification of large scale ASICs.
7. Strong scripting languages (Perl, C Shell, Makefile, ) experience.
8. Be good at English communication.

职位发布者

Jessy

7天

简历处理用时

89%

简历及时处理率

上海芯海集成电路设计有限公司

上海芯海集成电路设计有限公司

领域: 消费电子,通信网络

规模: 50-100人

主页: http://www.chipsea-design.com

工作地址:

上海/北京/深圳/成都/西安

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