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上海芯海集成电路设计有限公司

Analog Layout Engineer

  • 18万-30万/年
  • 上海
  • |
  • 3年以上
  • |
  • 本科
  • |
  • 全职

职位诱惑: 五险一金,福利好,老板nice

发布时间: 2017-03-24发布

职位描述

Location:Shanghai/Beijing/Shenzhen/Chengdu/Xi'an/Suzhou

Description:
1.    Full custom analog layout/verification and RC extraction.
2.    Perform block level layout. Conduct physical verification (DRC and LVS using Cadence tools).
3.    Team work with analog designers, optimize layout.
 
Qualification:
1.     Bachelor or above degree with 2+ years experiences in CMOS IC full-custom layout.
2.     Familiar with layout skills and knowledge is must.
3.     Good teamwork/communication/positive is must.
4.     Familiar with Cadence IC layout and verification tools
5.     Having massive IP block experience
6.     Familiar with below 40nm CMOS process and design rule is a plus.
7.     Familiar with ESD/Latch up and related layout solutions is a plus.
8.     Familiar with rule deck is a plus.
 

职位发布者

Jessy

Account Manager

7天

简历处理用时

89%

简历及时处理率