关注微信 意见反馈

扫描关注摩尔人半导体招聘

摩尔人招聘
确定
查看帮助中心
哎呀,这个职位已经下线啦
上海芯海集成电路设计有限公司

Package Design Engineer

  • 18万-36万/年
  • 上海
  • |
  • 3年以上
  • |
  • 本科
  • |
  • 全职

职位诱惑: 五险一金,福利好,老板nice

发布时间: 2017-03-24发布

职位描述

Location:Shanghai/Beijing
Summary of Role: Package Design Engineer is responsible for large scale ASIC package definition, package model extraction, system‐module SI/PI co‐simulation and thermal/reliability solution. Support ASIC chip designs on IO planning based on 32nm, 14nm and beyond technology. Design of high‐speed package escape patterns and power delivery structures. Manage ASIC package laminate design from definition to manufacture. Explore advanced package solutions such as 2.5D, 3D package. Development of tools in support of image/package/PCB co‐design.
Responsibilities: Work scope includes but not limited to:
‐ Package solution consulting and evaluation during project bid stage
‐ Define package netlist based on chip‐package co‐design methodology
‐ IO planning together with physical designer
‐ Package ERC checking, package design file checking
‐ Support customer on system‐module SI/PI co‐simulation
‐ Package design sign‐off ‐ Develop package design methodology in China Design Center
‐ Develop advanced 2.5D, 3D package design solution
The candidate would also have future extended responsibility participating in the design planning and sizing for the advanced ASIC/SoC chips, deployment and other application engineering support of the design methodology. 
 Requirements: 
1. EE/ME/CS related background in system/chip design
2. Solid knowledge and extensive industry experience in one or more of the following areas:
‐ High speed package/system design experience (High Speed Serdes, HBM, DDR, etc...)
‐ Familiar with Industry SI/PI analysis process, system level modeling and finite element analysis tools (Ansys HSFF, Sigrity, SigXp, Spice, MATLAB, etc...)
‐ Multiple players PCB/Laminate (4+) layout experience (Experience with automation, such as cadence APD and related design tools, and SKILL language programming is a plus)
3. Good grasp of Perl/TCL scripts under Linux/Unix environment. C programming will be a plus.
4. Good communication skill in both English and Mandarin, and willingness to work with a global team. Skill in other languages is a plus.
5. Understanding of ASIC physical design process/tools, advanced semiconductor technology process and device physics is a plus
6. Strong teamwork sense, good learning competency, self‐motivated, and ability to work in diverse areas in a flexible and dynamic environment. Preferred Qualifications:
Direct package engineer role with industry experience 

职位发布者

Jessy

Account Manager

7天

简历处理用时

86%

简历及时处理率