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上海芯海集成电路设计有限公司

Logic Verification Engineer/Manager

  • 21.6万-42万/年
  • 上海
  • |
  • 3年以上
  • |
  • 本科
  • |
  • 全职

职位诱惑: 年终奖金,五险一金,福利好,老板nice,技术领先,成长空间大,技能培训,年底双薪,年度旅游,节日礼物

发布时间: 2018-03-27发布

职位描述

Logic Verification Engineer/Manager
Location: Shanghai, Beijing
Responsibilities:
Logic Verification Engineer is working on cuttingedge Digital and Mixedsignal IP development for worldwide clients, including High Speed Serial Links, Protocols, Memory Interface, etc. By employing the industry leading tools, state of the art methodology, and innovative semiconductor leading technologies ranging from 32nm to 14nm and beyond, you will be participating in the frontend logic verification or mixed signal verification.
Requirements:
1. ME/EE/CS or background in related areas.
2. Research and/or development experience in one or more of the following areas:
● Logic verification on the basis of the target system specification
● Mixed signal model verification on advanced technologies
● Proficiency in programming and/or scripting languages is a plus
● Knowledge on Protocols, High Speed Serdes or DDR is a plus
3. Experience in one or more of the following application domains, is a plus
● High performance computing system, processor, chipset and ASICs
● High end communication, networking, mobile and data center applications
● Digital signal processing, sensor and Internet of Things
● Other emerging IT technology and industry areas
4. Good English skills, communication skills, and willingness to work with a global team.
5. Good learning competency, selfmotivated, and ability to work in diverse areas in a flexible and dynamic environment.

职位发布者

Jessy

Account Manager

7天

简历处理用时

74%

简历及时处理率