Staff Design Verification Engineer
Marvell Switching Chip Design team delivers industry leading high performance switching products that serve the data center networking and connectivity. You'll be working with the global team on Switching chip development, driving and manage subsystem/Chip level verification, and provide deployment support to various global products and teams
ü Work with architecture and designers to get a full deep insight on the design under verification.
ü Subsystem/Chip level state of the art verification, test bench setup/maintain and methodology deployment
ü Test case creation to ensure coding coverage meet target
ü Provide clear status of chip verification progress and issues to management.
ü Help Manager to ramp-up verification team.
ü Candidate is preferred to be MSEE with minimum of 5+ years, or BSEE with minimum of 7+ year experience in digital ASIC/SOC design verification.
ü As a team lead of Verification, the capability of mentor people and deliver high QoR in project are preferred to.
ü Good knowledge of Verilog/SV/UVM
ü C/C++/System C is a plus.
ü Modern Verification experience, random techniques, reference models etc.
ü Verification of large scale ASICs.
ü Verification in chip/SOC/system level.
ü Hands-on experience on Object Oriented verification such as UVM/OVM.
ü Good understanding of simulators.
ü Strong cooperation skill with global team. Experience of team lead is plus
ü Experience of tape-out using 28nm or advanced technology is plus
ü Strong self-motivation
ü Be open minded, passion and strong drive.
ü Excellent team work is required.