Campus Recruitment - Design Verification Engineer
ASIC design verification engineer responsible for the verification and evaluation of digital circuits in high-speed data communication ICs. The candidate will be involved in verification plan development, test environment setup, modeling, testcase development and execution. He/She will be responsible for block and /or chip level verification.
MS in EE or CE with VLSI emphasis. Graduate from reputable university with competitive GPA or class ranking. Graduate course work in VLSI design, digital circuit theory, logic design or computer architecture. Exposure to graduate school projects in ASIC design or verification.
Must be proficient in the following skills:
Fundamental concepts in digital logic design
Understand ASIC verification flows and methodologies
Verilog and SystemVerilog/SystemC/Vera
Strong Perl and Tcl scripting
UNIX Shell scripting (Csh, Bash)
Highly desirable skills:
Low power design
MATLAB and C/C++ based system simulation and evaluation
DSP function hardware implementation knowledge
Good personal communication skills and team working spirit. Hardworking and motivated to be part of a highly competent design team.