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Synopsys

ASIC Digital Design Manager

  • 50万-80万/年
  • 上海
  • |
  • 10年以上
  • |
  • 本科
  • |
  • 全职

职位诱惑: 年终奖金,五险一金,技术领先,成长空间大,技能培训

发布时间: 2019-08-02发布

职位描述

Job Title: ASIC Digital Design Manager
Location: Shanghai

Job Description :
This is a management position in IP development for semiconductor design
- Manage an IP development team and capable of working as a technical lead
- Define block micro-architecture according to architecture requirement
- Follow internal design flow to complete RTL design and documentation
- Work with verification team to debug and fix RTL design issues
- Use front-end EDA tools to make sure design can meet requirements
- Analyze synthesis results and update RTL design to meet timing if required
- Communicate and cooperate with global teams

Requirement:
- MS degree in EE with 10+ years working experience in ASIC design
- Expert in RTL design and experience in IP verification
- Familiar with EDA tools, including Spyglass, DC/DCT, Formality and PT
- Strong desire to learn and explore new technologies
- Good analysis and problem-solving skills
- Good communication skill is a must
- Prior R&D management experience is highly desired
- Knowledge in DDR and interface technologies such as PCIe, USB is a plus
- Knowledge in AMBA protocols is a plus

职位发布者

HR

7天

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97%

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