ASIC Physical Design Engineer
1. Work with global Front-End design team and physical design team for large scale ASIC GPU chips implementation.
2. Focus on RTL-Synthesis-physical design methodology optimize/update to improve fullchip Power/Performance (PPA), including block level (full chip) RTL- Synthesis -place&route power optimizing.
3. The individual is expected to be an expert in multiple aspects in Front-End or PD areas, should have RTL coding experience or Design Verification or Physical Design knowledge, at least one of the three areas.
4. The individual is also expected to be accountable for project delivery.
1. MSEE with 2+ years or Bachelor with 4+ years of industrial experience in ASIC design
2.2+ years or more years of experience in Physical Design or Design Verification in digital IC design
3. Familiar with low-power design
4. Familiar with Front-End or Back-End EDA tools
5. Hands on experience in large scale ASIC chip physical design
6. Knowledgeable in all aspects of deep submicron ASIC design flow
7. Successfully gone through several complete product development cycles
8. Good listening, writing and speaking English
9. Good communication skills, Dedicated, hardworking and good team player
10. Good at tcl / perl scripts