欢迎直接登陆51job NVIDIA 2020校园招聘网申系统申请，谢谢
We have multiple directions for ASIC Engineer development, including IP design/verification, SOC design/verification, ASIC Physical Design, DFT Design, FPGA/Emu, etc. We share them in a single JD
What you’ll be doing:
- Micro architecture design.
- RTL (Verilog) coding.
- Design implementation using Synopsys/Cadence tools.
- Simulate, debug and write tests to verify design functionality and performance. (IP/SOC/FPGA/EMU design/verification direction)
- Synthesis/Netlist quality check/Formal verification, Chip partitioning, Timing constraints development for various function/dft modes, Co-work with PR on floorplan and achieve timing closure, Timing sign off. (PD Direction)
- Responsible for DFT verification environment setup, own DFT verification and bringup tasks for Clocks, Boundary Scan, Analog and MBIST, Scan, etc. (DFT Direction)
- FPGA/EMU synthesis, partitioning and emulating using Synopsys/Cadence etc. Tools and FPGA/EMU ‘s infrastructure flow implementation (FPGA/ EMU direction)
- Methodology in any of above areas.
- MS degree from EE/CS or related majors from a prestigious university.
- Good knowledge in digital circuit design.
- Experience in using Verilog HDL.
- Experience in various of ASIC EDA tools.
- Fluent in English reading and writing.
- Self-motivated, good team player.
- Proven ability to work independently as well as in a multi-disciplinary group environment
- Good command of C/C++ programming language.
- Mastery in one of the below areas
- Video codec.
- Processor architecture.
- Signal/image processing.
- Pattern recognition/machine learning.
- Data science.
- System on Chip.
- Memory interface.
- Understand ASIC design flow, hands-on experience in using industrial standard EDA tools is a plus.
- Basic DFT knowledge including Boundary Scan, 1500, MBIST, Scan, ATPG is a plus
- Hand-on experience in EDA software from Synopsys (DC/PT/Formality), Cadence (RC compiler/LEC) is a plus
- Proficient user of script language like Perl, Python or TCL is plus
- Experienced in FPGA/EMU related implementation is a plus
- Experienced in Linux PCIE driver or other SW works is a plus
- Experienced in SystemC or UVM or SV or SCE-MI or other standards is a plus