Principal Design Engineer - FPGA
- 40万-60万/年
- 上海
- |
- 5年以上
- |
- 本科
- |
- 全职
职位诱惑: 年终奖金,福利好,老板nice,年底双薪,股票期权,技术领先
发布时间: 2019-12-09发布
职位描述
Title: Principal Design Engineer
Job Description
Responsible for designing and developing sub-systems and modules or components of hardware based verification products. In addition modifying, updating and productizing existing hardware based verification products. Perform as individual contributor on FPGA based design projects involving board design, RTL design, verification, productizing and documentation. Work on diverse problems related to FPGA design, simulation or verification issues.
Position Requirements:
The position requires BSEE, or equivalent, with a minimum of 5 yrs of industry experience in designing hardware systems.
Must have excellent communication skills, both written and verbal.
Technical expertise in FPGA design for either Altera or Xilinx products is required.
Experience in FPGA design methodologies including high speed design, serial protocols and FPGA timing closure is desired.
RTL design knowledge using Verilog is required along with experience in using RTL verification tools and flows.
Verification using with Cadence simulation products is desired.
Experience with scripting languages like Perl, TCL C-shell is strongly recommended.
Experience with PCB tools is also desired.
职位发布者
cadence hr
Sr.Manager&BP
简历处理用时
简历及时处理率
Cadence
领域: 移动手持,消费电子,通信网络
规模: 500-1000人
主页: http://www.cadence.com.cn/
工作地址:
上海市 浦东新区 前滩世贸中心3期
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