(Sr.)Digital Manager

Responsibilities:

1. Leading digital design team to design and implement high-speed SERDES IPs

2. Leading digital design team to perform algorithm design, RTL coding, analog design modeling, design verification, synthesis, timing closure, emulation and debugging of chips

3. Working with rest of Analog design team for interface definitions.

4. Working with the verification team to enable integration into top level test environments and provide support via functional models

5. Collaborating with the product development team to get the product into high volume applications

6. Mentoring junior engineers

Qualification:

1. MSEE/CS with at least 10+ years of IC digital design experience

2. Hands-on experience with 10Gbps and above SerDes is a plus

3. Very strong skills in Verilog RTL coding and simulation

4. Strong skills in scripting (C, Perl, Skill, MATLAB)

5. Self-motivated, good team work spirit and good communication skills

6. Relevant experiences in high speed SerDes IO design; Ethernet/PCIe/SATA/USB/MIPI is a plus